In a display device using ferroelectric liquid crystal or plasma display as the electro-optic element, the obtained luminance condition of the display device often varies due to variation of condition such as a manufacturing condition of each electro-optic element, even though the supplied voltage or pulse width is identical. Particularly, in a matrix-type display device whose pixels are adjacently aligned, the variation of the luminance condition greatly affects the display quality. For this reason, in a display device using a driving method of setting one display state in one frame period, there is a difficulty to obtain a required display quality in such electro-optic elements.
In view of the foregoing problem, a conventional matrix-type display device using such electro-optic elements is arranged to perform time division gradation display, which carries out switching of display state of an electro-optic element capable of finite R-gradation display, so that the display state changes more than once in one frame period and therefore realizes a desired B-gradation (B>R) display. For example, here, an extreme example of the time division gradation display is referred for ease of understanding. According to the example, one frame period is equally divided by two, and electro-optic elements (R=2) capable of 2-gradation display are independently controlled their lighting in the first half period and the second half period, so as to realize 3-gradation display (this provides light quantity levels of 0, 1, 2, i.e., B=3). Further, since this time division gradation display does not decrease fineness of the display, it is effective to realize multi-gradation display.
FIG. 16 is a drawing showing a driving method disclosed in a patent document 1 (EPA0261901A2: published on Mar. 30, 1988), which is a typical conventional technology for realizing such a time division gradation display. The configuration of the patent document 1 adopts ferroelectric liquid crystal as an electro-optic element, and the respective electro-optic elements carry out 2-gradation display (R=2), and further, each of the display state is switched 4 times in one frame period so as to realize 16-gradation display (B=16). The example of FIG. 16 assumes a matrix-type display device in which 15 scanning lines (G1 through G15) are controlled together as one group. Hereinafter, 4 bits data displayed in each electro-optic element will be respectively referred to as first bit data, second bit data, third bit data, and fourth bit data, in order-of lighter to heavier in the weight of data.
The horizontal axis of the figure denotes time, and (1) denotes total time of selection time, having a minimum unit, and 60 selection times make up one frame period. (2) denotes the time, which is obtained by dividing the one frame period into control units, and one frame period includes 15 unit times. Further, (3) denotes occupied time of each bit data in the unit time, i.e., timing slots for practically outputting each bit data to a data line. The occupied time is made up of 4 slots (1 through 4). Further, (4) through (18), which denote the data displayed in the respective scanning lines G1 through G15, and a number “1” is shown when the first bit data is displayed, a number “2” is shown when the second bit data is displayed, a number “3” is shown when the third bit data is displayed, and a number “4” is shown when the fourth bit data is displayed, as the data firstly displayed in the display period of each data.
Accordingly, in the scanning line G1, for example, operation of 1 frame is carried out in such a manner that: the scanning line G1 is firstly selected the first occupied time of the first unit time, and the first bit data is displayed during the first selection time through the fifth selection time, then the G1 is secondly selected in the second occupied time of the second unit time, and the second bit data is displayed during the sixth selection time through the fourteenth selection time, then the G1 is thirdly selected in the third occupied time of the fourth unit time, and the third bit data is displayed during the fifteenth selection time through the thirty first selection time, and further, the G1 is lastly selected in the fourth occupied time of the eighth unit time, and the fourth data is displayed during the thirty second selection time through the sixty fourth selection time.
However, in this configuration of the patent document 1, respective weights of the first through fourth bits are 1:2:4:8 in the unit time; and are 5:9:17:29 in the selection time, which shows some errors especially in lower bits. Thus, there arises a problem of inadequate accuracy. Further, the number of the scanning lines is always required to be Σ2K−1 (k=0, 1, 2) in each group so as to realize this arrangement.
In this point of view, another patent document (patent document 2; U.S. Pat. No. 5,969,713: issued on Oct. 19, 1999) will be explained as an example for solving the foregoing problem. FIG. 17 is a drawing showing a driving method described in Example 1 of the patent document 2. In this configuration of the patent document 2, each electro-optic element is made up of two partial pixels having area ratio of 1:2, and the respective electro-optic elements carry out 2-gradation display so as to realize 4-gradation display (R=4), and further, each of the display state is switched 3 times in one frame period so as to realize 64-gradation display. The example of FIG. 17 assumes a matrix-type display device in which scanning lines G1 through G7 are controlled as one group.
The horizontal axis of the figure denotes time, and (1) denotes total time of selection time (a minimum unit), and 21 selection times make up one frame period. (2) denotes unit time, which is decided by dividing the one frame period into control units, and one frame period includes 7 unit times. Further, (3) denotes occupied time of each bit data in the unit time. The occupied time is made up of 3 slots (1 through 3). Further, (4) through (10), which denote the data displayed in the respective scanning lines G1 through G7.
Accordingly, in the scanning line G1, for example, operation of 1 frame is carried out in such a manner that: the scanning line G1 is firstly selected in the first occupied time of the first unit time, and the first bit data is displayed only in the first selection time since the G1 is secondly selected in the second occupied time of the first unit time; and then the second bit data is displayed during the second selection time through the fifth selection time since the G1 is thirdly selected in the third occupied time of the second unit time, and the third bit data is displayed in the sixth selection time through the twenty first selection time.
In terms of the selection time, this manner realizes gradation display in which the display term ratio of 1:4:16 with respect to each bit is accurately consistent with the weight of the bit.
Further, FIG. 18 is a drawing showing a driving method described in Example 2 of the patent document 2. In this configuration, each electro-optic element carries out two gradations display (R=2), and each of the display state is switched 3 times in one frame period. The example of FIG. 18 assumes a matrix-type display device in which scanning lines G1 through G8 are controlled as one group.
The horizontal axis of the figure denotes time, and (1) denotes the total time, and 24 selection times make up one frame period. (2) denotes the unit time, and one frame period includes 8 unit times. Further, (3) denotes the occupied time, which is made up of 3 slots (1 through 3). Further, (4) through (11), which denote the data displayed via the respective scanning lines G1 through G8.
Accordingly, in the scanning line G1, for example, operation of 1 frame is carried out in such a manner that: the scanning line G1 is firstly selected in the first occupied time of the first unit time, and the first bit data is displayed in the first selection time through the third selection time, then the G1 is secondly selected in the second occupied time of the second unit time, and the second bit data is displayed in the fifth selection time through the tenth selection time, then the G1 is thirdly selected in the third occupied time of the fourth unit time, and the third bit data is displayed in the twelfth selection time through the twenty third selection time. Further, blank data denoted by “B” is written in an occupied time before the occupied time where each bit data is set, apart from data condition of the data line, so as to carry out initialization by deleting all data of electro-optic elements which have been displayed.
As a result, the difference between (a) 24 selection times (8 scanning lines×3 numbers of bit) making up one frame period and (b) total display period of the first through third bit data, i.e., 21 selection times (=3+6+12) is provided as a blanking period, during which a non-display state occurs.
In terms of the selection time, this manner realizes gradation display in which the display term ratio 3:6:12=1:2:4=20:21:22 of each bit is accurately consistent with the weight of the bit.
Furthermore, gradation display of 1:2:4:8 is disclosed in other examples of the patent document 2, and they also describe an arrangement in which each period from the initialization by the blank data “B” to a display of the next bit data is increased to be 2 selection times or more, or, the period varies depending on the respective bits, so as to carry out group control for an arbitrary number of signal line other than multiples of 8. As thus described, by using the driving method disclosed in the patent document 2, it is possible to obtain a display term ratio proportional to the weight of each bit.
However, even though each gradation level in one frame period may be set to be a target one, the configuration of the patent document 2 has a problem of limitation of the number of scanning lines, or the arrangement of electro-optic elements.
More specifically, in the configuration disclosed in Example 1 of the patent document 2, when a gradation number displayable in one pixel is set to be R=4, the weight of each bit will be such as the foregoing ratio of 1:4:16 (1:R:R2), and therefore (the number of scanning lines×the number of bits) has to be a multiple of 21 (=1+4+16). In this point of view, since the other examples, i.e., the Example 2 and later examples adopt blank scanning, it is not required to limit (the number of scanning lines)×(the number of bits/ΣRn (summation of Rn (R: weight ratio)) to be an integer. However, those examples have a different limit of requirement of initialization scanning, which has to be carried out apart from the scanning for writing display data.
Here, the patent document 2 deals with a case of using ferroelectric liquid crystal as an electro-optic element, and therefore there are no difficulties to set the blank scanning. However, in the case of using other types of liquid crystal, such as TN (Twisted Nematic) liquid crystal, or in the case of using organic EL (Electro Luminescence), the arrangement requiring the blank scanning cannot be adopted. This gives rise to a problem.
To be more specific, in the ferroelectric liquid crystal, the liquid crystal is driven by a simple matrix driving and the blank display (initialization) can be realized by applying a voltage of negative polarity to a scanning line. Thus, it is possible to simultaneously select a scanning line for writing bit data for display, and a scanning line for the initialization. For example, in FIG. 18, in the first occupied time of the first unit time, the scanning line G1 is selected for the writing of data and therefore supplied with a voltage of positive polarity, and the scanning line G8 is selected for the initialization and therefore supplied with the voltage of negative polarity. In this manner, the blank scanning can easily be set without increasing the selection time.
On the other hand, in the case of using such as TN liquid crystal or organic EL, the initialization cannot be carried out in an asynchronous state only by changing the voltage applied to a scanning line. Thus, the TN liquid crystal or the organic EL requires an initialization TFT (Thin Film Transistor) for each electro-optic element, as disclosed in Japanese Laid-Open Patent Application Tokukai 2000-221942, or in Japanese Laid-Open Patent Application Tokukai 2001-242827, so as to carry out initialization scanning apart from the scanning for the writing of bit data for display. FIGS. 19 and 20 show this arrangement.
FIG. 19 shows an example of using liquid crystal other than the ferroelectric liquid crystal, as an electro-optic element. In this example, each bit data is outputted to a source line Sj, and supplied to an electro-optic element LCD via a gate TFT 1, which is selected by a gate line Gi. Then, the potential of the electro-optic element LCD is initialized to be the potential of an initialization line Dj via an initialization TFT 2, which is selected by an select line Ei.
Further, FIG. 20 shows an example of using organic EL, as an electro-optic element. In this example, each bit data is outputted to a source line Sj, and supplied to a capacitor C via a gate TFT 1, which is selected by a gate line Gi. The source-drain resistance of a driving TFT 3 is changed due to the potential of the capacitor C, and the current flowing from a power source line Pj to an optical element LED is set. Then, as with the arrangement of FIG. 19, the potential of the capacitor C is initialized to be the potential of the power source line Pj via an initialization TFT 2, which is selected by an select line Ei.
As described above, the application of the second driving method of the patent document 2 to an active matrix display device arises a problem that the initialization TFT 2, the select line Ej, and the initialization line Dj should be separately provided. In a liquid crystal display device having this arrangement, the aperture ratio is reduced, which causes a decrease of luminance efficiency particularly in a liquid crystal panel using a backlight. Further, in an organic EL display device having the foregoing arrangement, the luminance area is reduced, and therefore greater luminance is required for obtaining a target luminance for the entire panel, thus shortening the life of the elements.